View SM89T16R1C25_3333594.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89t16r1 08/2006 1 product list sm89t16r1l16, 16mhz 64kb internal flash mcu SM89T16R1C25, 25mhz 64kb internal flash mcu general description the sm89t16r1 is a high speed (4 clocks / machine cycle) single-chip 8-bits microcontroller manufactured in an advanced cmos process with on chip flash memory. it supports a derivative of the 80c51 microcontroller family. the sm89t16r1 has the same instructions set as the 80c51. the sm89t16r1 contains a 64kb on chip program flash, a volatile 1280 x 8 bits data ram, four 8-bits i/o ports, one 4-bits i/o port, two 16-bits timer/event counters, and an additional 16-bits timer coupled to capture and compare latches, a two-priority-level, nested interrupt structure, two pulse-width- modulation outputs, two uart and two dptr, an on-chip oscill ator and timing circuit. for system that requires extra capability the sm89t16r1 can be expanded using standard ttl compatible memory and logic. in addition, the sm89t16r1 has two software selectable modes of pow er saving ? idle mode and power-down mode. the idle mode freezes the cpu while allowing the ram, timer, serial ports, and interrupt system to continue functioning. the power-do wn mode saves the ram contents but freezes the oscillator, causing all other chip functions to be inoperative. the power management mode (pmm) is useful for portable or battery-powered applications. this feature allows software to select a lower speed clock as the main time base. ordering information sm89t16r1ihhkl yymmv i: process identif ier {l=3.0v~3.6v,c=4.5v~ 5.5v} hh: working clock in mhz {16,25} k: package type postfix {as below table} yy: year mm: month v: version identifier { , a, b, ...} l: pb free identifier {no text is non-pb free,?p? is pb free} feature z working voltage: 3.3v or 5.0v. z 80c51 central processor unit (cpu), high-speed architecture (4 clocks / machine cycle), the maximum clock rate is 25 mhz. z 64k x 8 on chip flash memory can be programmed at v pp = 12v z 1280 x 8 ram (on-chip 256 bytes and expand 1024 bytes), expandable externally to 64kb z two standard 16-bits timers/counters z an additional 16-bits timer/counter coupled to a capture and compare register. z two 8-bits / 5-bits resolution pulse-width-modulation (pwm) outputs. z four channels 6 bits analog to digital converter (adc). z four 8-bits i/o ports.(for pdip package) z four 8-bits i/o ports pl us one 4-bits i/o port. (for plcc or pqfp package) z two full-duplex enhance uart z two dptr (either data pointer can be incremented and decrement). z 13 interrupt sources (default 6 + int2, int3, int4, int5, uart1, adc, rtc) with 2 priority levels. z rtc (real time clock) function. z extended temperature range (-40 to +85 ) z software enable/disable ale output pulse z wake-up from powe r-down mode by external interrupt, rtci or h/w reset. taiwan 6f, no.10-2 li- hsin 1st road , science-based industrial park, hsinchu, taiwan 30078 tel: 886-3-567-1820 886-3-567-1880 fax: 886-3-567-1891 886-3-567-1894
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89t16r1 08/2006 2 pin configuration figure 1 44l pqfp package pwm1/#int3/p1.5 p0.4/ad4 int4/p1.6 p0.5/ad5 #int5/p1.7 p0.6/ad6 res p0.7/ad7 rxd/p3.0 #ea p4.3 p4.1 txd/p3.1 ale/x32out #int0/p3.2 #psen/x32in #int1/p3.3 p2.7/a15/adc3 t0/p3.4 p2.6/a14/adc2 t1/p3.5 p2.5/a13/adc1 pwm0/int2/p1.4 p3.6/#we txd1/p1.3 p3.7/#rd rxd1/p1.2 xtal2 t2ex/p1.1 xtal1 t2/p1.0 vss p4.2 p4.0 vdd p2.0/a8 ad0/p0.0 p2.1/a9 ad1/p0.1 p2.2/a10 ad2/p0.2 p2.3/a11 ad3/p0.3 p2.4/a12/adc0 1 234567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 26 25 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 figure 3 40l pdip package pwm1/#int3/p1.5 pwm0/int2/p1.4 txd1/p1.3 rxd1/p1.2 t2ex/p1.1 vdd p2.0/a8 p2.1/a9 p0.1/ad1 p2.2/a10 p0.2/ad2 p2.3/a11 p0.3/ad3 p2.4/a12/adc0 int4/p1.6 #int5/p1.7 res rxd/p3.0 txd/p3.1 #int0/p3.2 #int1/p3.3 t0/p3.4 t1/p3.5 #we/p3.6 #rd/p3.7 xtal2 xtal1 vss p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ale/x32out #psen/x32in p2.7/a15/adc3 p2.6/a14/adc2 p2.5/a13/adc1 p0.0/ad0 #ea 40 t2/p1.0 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 package spec. package pin / pad frequency 44l pqfp figure 1 16 mhz at 3.3v and 25mhz at 5v 44l plcc figure 2 16 mhz at 3.3v and 25mhz at 5v 40l pdip figure 3 16 mhz at 3.3v and 25mhz at 5v figure 2 44l plcc package pwm1/#int3/p1.5 p0.4/ad4 int4/p1.6 p0.5/ad5 #int5/p1.7 p0.6/ad6 res p0.7/ad7 rxd/p3.0 #ea p4.3 p4.1 txd/p3.1 ale/x32out #int0/p3.2 #psen/x32in #int1/p3.3 p2.7/a15/adc3 t0/p3.4 p2.6/a14/adc2 t1/p3.5 p2.5/a13/adc1 p1.4/int2/pwm0 #we/p3.6 p1.3/txd1 #rd/p3.7 p1.2/rxd1 xtal2 p1.1/t2ex xtal1 p1.0/t2 vss p4.2 p4.0 vdd a8/p2.0 p0.0/ad0 a9/p2.1 p0.1/ad1 a10/p2.2 p0.2/ad2 a11/p2.3 p0.3/ad3 adc0/a12/p2.4 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89t16r1 08/2006 3 block diagram p0 p1 p2 p3 parallel i/o ports & ext. bus p4 adc0 ( 2 ) uart int-ram 256x8 timer0 timer1 cpu flash 64kx8 ext-ram 1024x8 adc pwm timer2 ibus c51 core wr res t0 t1 (3) (3) int / pdwu int0 int1 (3) (3) port0 port1 port2 port3 adc1 ( 2 ) (3) rd (3) psen ale xtal2 xtal1 ea pwm1 pwm0 (1) (1) t2ex t2 (1) (1) notes: (1): alternate function of p1 (2): alternate function of p2 (3): alternate function of p3 (4): alternate function of ale, psen expand interrupt/ wake up adc2 ( 2 ) adc3 ( 2 ) rxd txd (3) (3) txd1 rxd1 (1) (1) int2 (1) int3 (1) int4 (1) int5 (1) uart1 rtc port4 x32in x32out (4) (4)
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89t16r1 08/2006 4 pin description mnemonic dip 40 pin pqfp 44 pin plcc 44 pin names and functions vdd 40 38 44 power supply : +3.3v and +5v power supply pin dur ing normal operations and power saving modes. p0.0 ? p0.7 39,38,37,36 35,34,33,32 37,36,35,34 33,32,31,30 43,42,41,40 39,38,37,36 port 0 : port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them become floating and can be used as high- impedance inputs. port 0 is also the multiple xed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pull-ups when emitting 1s. port pin alternative function p0.0 ad0 p0.1 ad1 p0.2 ad2 p0.3 ad3 p0.4 ad4 p0.5 ad5 p0.6 ad6 p0.7 ad7 p1.0 ? p1.7 1,2,3,4, 5,6,7,8 40,41,42,43, 44,1,2,3 2,3,4,5, 6,7,8,9 port 1: an 8-bits bidirectional i/o port with internal pull-ups on all pins. port 1 pins that have 1s written to them ar e pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: iil). alternate function of sm89t16r1 include: port pin alternative function p1.0 t2: timer2 clock output p1.1 t2ex: timer2 reload/capture dir. p1.2 rxd1: uart1 input p1.3 txd1: uart1 output p1.4 pwm0: pwm channel 0 output int2: rising edge trigger p1.5 pwm1: pwm channel 1 output #int3: falling edge trigger p1.6 int4: rising edge trigger p1.7 #int5: falling edge trigger rst 9 4 10 reset : a high on this pin for two machine cy cles while the os cillator is running resets the device. an internal resistor to vss permits a power-on reset using only an external capacitor to vcc. p2.0 ? p2.7 21,22,23,24, 25,26,27,28 18,19,20,21 22,23,24,25 24,25,26,27, 28,29,30,31 port 2: port 2 is an 8-bits bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pu lled high by the internal pull-ups and can be used as inputs. as inputs, por t 2 pins that are externally being pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: iil). port 2 emits the high-order address byte during fetches from external prog ram memory and during accesses to external data memory that uses 16-bits addresses (movx @dptr). in this application, it uses strong inte rnal pull-ups when emitting 1s. during accesses to external data memory that uses 8-bits addresses (mov @ri), port 2 emits the contents of the p2 special function register. port pin alternative function p2.0 a8 p2.1 a9 p2.2 a10 p2.3 a11 p2.4 a12/adc0 p2.5 a13/adc1 p2.6 a14/adc2 p2.7 a15/adc3 mnemonic dip 40 pin pqfp 44 pin plcc 44 pin names and functions
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89t16r1 08/2006 5 p3.0 ? p3.7 10,11,12,13 14,15,16,17 5,7,8,9, 10,11,12,13 11, 13,14,15, 16,17,18,19 port 3 : port 3 is an 8-bits bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pu lled high by the internal pull-ups and can be used as inputs. as inputs, por t 3 pins that are externally being pulled low will source current because of the pull-ups. (see dc electrical characteristics: iil). port 3 also serves the special features. port pin alternative function p3.0 rxd uart input p3.1 txd uart output p3.2 #ex0 external interrupt 0 p3.3 #ex1 external interrupt 1 p3.4 t0: timer 0 external input p3.5 t1: timer 1 external input p3.6 #wr external data memory write strobe p3.7 #rd external data memory read strobe ale/x32out 30 27 33 address latch enable : output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted twice every machine cycle, and can be used for ex ternal timing or clocking. note that one ale pulse is skipped during each access to external data memory. setting sfr sconf.0 can disable ale. with this bit set, ale will be active only dur ing a movx instruction. x32out: the 32.768khz crystal output for rtc function. #psen/x32in 29 26 32 program store enable: the read strobe to external program memory. when executing code from the external program memory, #psen is activated twice each machine cycle, except that two #psen activa tions are skipped during each access to external data memory. #psen is not activated during fetches from internal program memory. x32in: the 32.768khz crystal input for rtc function. #ea 31 29 35 external access enable : #ea must be externally held low to enable the device to fetch code from external program memory locations. if #ea is held high, the device executes from internal program memory. xtal1 19 15 21 crystal 1 : input to the inverting oscillator amp lifier and input to the internal clock generator circuits. xtal2 18 14 20 crystal 2 : output from the inverting oscillator amplifier. sfr mapping the special function regist er of sm89t16r1 fall into the following categories z c51 core register: acc, b, dpl, dph, psw, sp z i/o ports: p0,p1, p2, p3, p4 z timer/counter register: t2con, t2mod, tcon, tmod, th0, th1, th2, tl0, tl1, tl2, rca2pl, rcap2h z the second dptr register: dps, dph1, dpl1 z uart i/o register: sbuf, scon z uart1 i/o register: sbuf1, scon1 z adc register: adcsc, adcd, p2con z power and system control register: pcon, sconf z interrupt system register: ip, ie, ip1, ie1, ifr z expand external interrupt re gister: eie, eip, exif z rtc register: rtcc, rtcs z pwm output register: pwmc0, pwmc1, pwmd0, pwmd1, p1con z pmm (power management) register: pmr
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89t16r1 08/2006 6 table 1 sfr map $f8 scon1 0000 0000 sbuf1 xxxx xxxx $ff $f0 b 0000 0000 $f7 $e8 saden 0000 0000 saden1 0000 0000 $ef $e0 acc 0000 0000 $e7 $d8 p4 xxxx 1111 saddr 0000 0000 saddr1 0000 0000 $df $d0 psw 0000 0000 pmr 01xx 0000 pwmc0 0000 0000 pwmc1 0000 0000 $d7 $c8 t2con 0000 0000 t2mod 0000 0000 rcap2l 0000 0000 rcap2h 0000 0000 tl2 0000 0000 th2 0000 0000 $cf $c0 $c7 $b8 ip x000 0000 ip1 0000 0000 eip xxxx 0000 sconf 0000 0000 $bf $b0 p3 1111 1111 pwmd0 0000 0000 pwmd1 0000 0000 $b7 $a8 ie 0000 0000 ie1 0000 0000 ifr 0000 0000 eie 0000 0000 $af $a0 p2 1111 1111 rtcs 0000 0000 rtcc 0000 0000 ckcon 0000 0001 dpl1 0000 0000 dph1 0000 0000 dps 0000 0000 $a7 $98 scon 0000 0000 sbuf xxxx xxxx p1con 0000 0000 p2con 0000 0000 $9f $90 p1 1111 1111 exif 0000 1xxx ledp0 0000 0000 ledp1 0000 0000 ledp2 0000 0000 ledp3 0000 0000 ledp4 0000 0000 $97 $88 tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 adcsc 0000 0000 adcd 0000 0000 $8f $80 p0 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 pcon 00xx 0000 $87 table 2 all sfr list (adc, rtc, pwm, led driving capability control) symbol description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset a/d converter adcsc adc status & control 8eh com con adcss1 adcss0 ch1 ch0 00h adcd adc data register 8fh ad. 5 ad.4 ad.3 ad.2 ad.1 ad.0 00h real timer clock (rtc) rtcs rtc status a1h rtcen stable s ec.5 sec.4 sec.3 sec. 2 sec.1 sec.0 00h rtcc rtc control a2h int_sel.1 int_sel.0 min.5 min.4 min.3 min.2 min.1 min.0 00h pwm output pwmc0 pwm 0 control d3h pbs pfs1 pfs0 00h pwmc1 pwm 1 control d4h pbs pfs1 pfs0 00h pwmd0 pwm 0 data b3h pwmd.7 pwmd.6 pwmd.5 pwmd.4 pwmd.3 pwmd.2 pwmd.1 pwmd.0 00h pwmd1 pwm 1 data b4h pwmd.7 pwmd.6 pwmd.5 pwmd.4 pwmd.3 pwmd.2 pwmd.1 pwmd.0 00h led driving capability control ledp 0 led output in p0 92h 00h ledp 1 led output in p1 93h 00h ledp 2 led output in p2 94h 00h ledp 3 led output in p3 95h 00h ledp 4 led output in p4 96h 00h
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89t16r1 08/2006 7 table 3 : all sfr list (8051, i/o, timer, uart/uart1, system, interrupt) symbol description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset 8051 core acc* accumulator e0 00h b b register f0 00h sp stack pointer 81h 07h psw* process status d0h cy ac f0 rs1 rs0 ov p 00h dptr data pointer (2 bytes) dph data pointer high 83h 00h dpl data pointer low 82h 00h i/o port p0* port 0 80h p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 ffh p1* port 1 90h p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 ffh p2* port 2 a0h p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 ffh p3* port 3 b0h p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 ffh p4* port 4 d8h p4 .3 p4.2 p4.1 p4.0 xfh p1con p1 control 9bh pwm1e pwm0e - - 00h p2con p2 control 9ch adce3 adc e2 adce1 adce0 00h timer / counter tcon* timer control register 88h tf1 tf1 tf0 tr0 ie1 it1 ie0 it0 00h thl0 timer 0 (2 bytes) th0 timer 0 high 8ch 00h tl0 timer 0 low 8ah 00h thl1 timer 1 (2 bytes) th1 timer 1 high 8dh 00h tl1 timer 1 low 8bh 00h t2con* timer 2 control c8h tf2 exf2 rclk tclk exen2 tr2 ct2 cprl2 00h t2mod timer 2 mode control c9h hc5 hc4 hc3 hc2 t2cr t2oe dcen 00h rcap2hl reload/capture (2 bytes) rcap2h rcap2 high cbh 00h rcap2l rcap2 low cah 00h thl2 time 2 (2 bytes) th2 timer 2 high cdh 00h tl2 time 2 low cch 00h uart & uart1 scon* uart control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00h sbuf uart buffer 99h xxh scon1 uart 1 control f8h sm0_1/fe_1 sm1_1 sm2_1 ren_1 tb8_1 rb8_1 ti_1 ri_1 00h sbuf1 uart 1 buffer f9h xxh saddr slave address d9h 00h saddr1 slave address 1 dah 00h saden slave address mask enable e9h 00h saden1 slave address 1 mask enable eah 00h data point 1 dptr1 data pointer 1 (2 bytes) dph1 data pointer 1 high a5h 00h dpl1 data pointer 1 low a4h 00h dps data point select a6h dps.0 00h power and system pcon power control register 87h smod smod0 pd idle 00h sconf system control bfh smod1 pdwue ome alei 00h pmr power management register d1h cd1 cd0 xtoff 40h interrupt system ie* interrupt enable a8h ea es1 et2 es0 et1 ex1 et0 ex0 00h ie1 interrupt enable 1 a9h eadc ertc 00h ifr interrupt flag 1 aah adcif rtcif 00h eie external interrupt enable abh ex5 ex4 ex3 ex2 00h ip* interrupt priority b8h ps1 pt2 ps0 pt1 px1 pt0 px0 00h ip1 interrupt priority 1 b9h padc prtc 00h eip external interrupt priority bah px5 px4 px3 px2 x0h clock control ckcon clock control a3h t2m t1m t0m md2 md1 md0 01h
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89t16r1 08/2006 8 operating conditions symbol description min. typ. max. unit. remarks ta operating temperature -40 25 85 ambient temperature under bias vcc33 supply voltage 3.0 3.3 3.6 v vcc5 supply voltage 4.5 5.0 5.5 v fosc 16 oscillator frequency 16 mhz for 3.3v application fosc 25 oscillator frequency 25 mhz for 5.0v application dc characteristic v cc = 5v ( 10%), v ss =0v t a = -40 to 85 limits symbol parameter test conditions min max unit v cc supply voltage 4.5 5.5 v i cc supply current operating see notes 1 f clk = 12mhz v cc = 5.0v 30 ma i id supply current idle mode see note 2 f clk = 12mhz v cc = 5.0v 15 ma supply current power-down mode rtc disable see note 3 v cc = 5.5v 30 a i pd supply current power-down mode rtc enable see note 3 v cc = 5.5v 100 ua input v il1 input low voltage, p0, p1, p2, p3, p4, /ea -0.5 0.8 v v il2 input low voltage, res, xtal1 0 0.8 v v ih1 input high voltage, p0, p1, p2 , p3, p4, /ea 2.0 vcc+0.5 v v ih2 input high voltage, res, xtal1 70%vcc vcc+0.5 v i il input current low level port 1,2,3,4 vin = 0.45v -75 a i tl transition current high to low port 1,2,3,4 vin = 2.0 v -650 a i li input leakage current 0.45v < vin < vcc-0.3v 10 a output v ol1 output low voltage, port 0,ale, /psen iol = 3.2ma vcc=5.0v 0.45 v v ol2 output low voltage, port 1, 2, 3, 4 iol = 1.6ma vcc =5.0v 0.45 v v oh1 output high voltage port0 ale, /psen ioh = -800ua vcc =5.0v 2.4 v v oh1 output high voltage port 1,2,3,4 ioh = -60 a vcc =5.0v 2.4 v r rst internal reset pull-down resistor 50 300 k ? c io pin capacitance test freq=1mhz, ta=25 10 pf v cc = 3.3v ( 10%), v ss =0v , t a =-40 to 85 limits symbol parameter test conditions min max unit v cc supply voltage 3.0 3.6 v i cc supply current operating see notes 1 f clk = 12mhz v cc = 3.6v 20 ma i id supply current idle mode see note 2 f clk = 12mhz v cc = 3.6v 10 ma supply current power-down mode rtc disable see note 3 v cc = 3.6v 20 a i pd supply current power-down mode rtc enable see note 3 v cc = 3.6v 30 a input v il1 input low voltage, p0, p1, p2, p3, p4, /ea vcc = 3.6v 0 0.2 vcc -0.2 v v il2 input low voltage, rst,xtal1 vcc = 3.6v 0 0.2 vcc -0.2 v vih1 input high voltage, p0, p1, p2, p3, p4, /ea vcc = 3.6v 0 0.2 vcc -0.2 v vih2 input high voltage, rst vcc = 3.6v 0.6 vcc -0.4 vcc + 0.2 v vih3 input high voltage, xtal1 vcc = 3.6v 0.6 vcc vcc + 0.2 v
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89t16r1 08/2006 9 -0.4 iin1 input current low level port 1,2,3,4 vcc = 3.0v ~3.6v, vin = 0.45v. -10 50 a itl transition current high to low port 1,2,3,4 see note 4 vcc = 3.6v, vin = 1.2 v -75 400 a ili input leakage current p0, /ea vcc = 3.0v ~3.6v, 0.45v 100pf), the noise pulse on the ale pin may exceed 0.8v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an addre ss latch with a schmitt trigger strobe input.
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89t16r1 08/2006 10 ac characteristic v cc =3.3v 10%, v ss =0v, t clk min = 1/ f max (maximum operating frequency) t a =-40 to +85 c l =100pf for port0, ale and /psen; c l =80pf for all other outputs unless otherwise specified. symbol figure parameter min max unit external clock drive into xtal1 t clcl 4 xtal1 period 62.5 (1) - ns t chcx 4 xtal1 high time 31 - ns t clcx 4 xtal1 low time 31 - ns t clch 4 xtal1 rise time - 15 ns t chcl 4 xtal1 fall time - 15 ns t cyc 4 controller cycle time = t clcl / 4 5.2 - ns notes: 1. operating at 25mhz. symbol figure parameter min max unit program memory 1/t clcl 7 system clock frequency 3.0 16 mhz t lhll 7 ale pulse width 1.5 t clcl -5 ns t av l l 7 address valid to ale low 0.5 t clcl -5 ns t llax 7 address hold after ale low 0.5 t clcl -5 ns t llax 8 address hold after ale low for movx write 0.5 t clcl -5 ns t lliv 7 ale low to valid instruction in 2.5t clcl -20 ns t llpl 7 ale low to /psen low 0.5 t clcl -5 ns t plph 7 /psen pulse width 2.0 t clcl -5 ns t pliv 7 /psen low to valid instruction in 2.0t clcl -20 ns t pxix 7 input instruction hold after /psen 0 ns t pxiz 7 input instruction float after /psen t clcl -5 ns t av i v 1 7 port 0 address to valid instruction in 3.0t clcl -20 ns t av i v 2 7 port 2 address to valid instruction in 3.5t clcl -20 ns t plaz 7 /psen low to address float 0 ns movx characteristics using stretch memory cycles symbol figure parameter min max unit stretch t lhll2 8 ale pulse width 1.5 t clcl ?5 2.0 t clcl -5 ns t mcs =0 t mcs >0 t llax2 9 address hold after ale low for movx write 0.5 t clcl -5 ns t rlrh 8 /rd pulse width 2.0 t clcl ?5 t mcs -10 ns t mcs =0 t mcs >0 t wlwh 9 /wr pulse width 2.0 t clcl ?5 t mcs -10 ns t mcs =0 t mcs >0 t rldv 8 /rd low to valid data in 2.0 t clcl ?20 t mcs -20 ns t mcs =0 t mcs >0 t rhdx 8 data hold after /rd 0 ns t rhdz 8 data float after /rd t clcl ?5 2.0 t clcl ?5 ns t mcs =0 t mcs >0 t lldv 8 ale low to valid data in 2.5 t clcl ?5 t mcs +2.0t clcl ?40 ns t mcs =0 t mcs >0 t av i v 1 8 port 0 address to valid instruction in 3.0 t clcl -20 2.0 t clcl ?5 ns t mcs =0 t mcs >0 t av i v 2 7,8 port 2 address to valid instruction in 3.5 t clcl -20 2.5 t clcl ?5 ns t mcs =0 t mcs >0 t llwl 8,9 ale low to /rd or /wr low 0.5 t clcl ?5 1.5 t clcl ?5 0.5 t clcl +5 1.5 t clcl +5 ns t mcs =0 t mcs >0 t av w l 1 8,9 port0 address valid to /wr or /rd low t clcl ?5 2.0 t clcl ?5 ns t mcs =0 t mcs >0 t avdv2 9 port2 address valid to /wr or /rd low 1.5t clcl ?5 ns t mcs =0
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89t16r1 08/2006 11 2.5 t clcl ?5 t mcs >0 t qvwx 9 data valid to /wr transition -5 1.0 t clcl -5 ns t mcs =0 t mcs >0 t whqx 9 data hold after /wr 1.0 t clcl -5 2.0 t clcl -5 ns t mcs =0 t mcs >0 t rlaz 8 /rd low to address float 0.5 t clcl ?5 ns t whlh 8,9 /rd or /wr high to ale high 0 1.0 t clcl -5 10 1.0 t clcl +5 ns t mcs =0 t mcs >0 notes: t mcs i s time period related to the stretc h memory cycle selection. the fo llowing table shows the value of t mcs for each stretch selection. m2 m1 m0 movx cycles t mcs 0 0 0 2 machine cycles 0 0 0 1 3 machine cycles 4 t clcl 0 1 0 4 machine cycles 8 t clcl 0 1 1 5 machine cycles 12 t clcl 1 0 0 6 machine cycles 16 t clcl 1 0 1 7 machine cycles 20 t clcl 1 1 0 8 machine cycles 24 t clcl 1 1 1 9 machine cycles 28 t clcl parameter figure symbol min typ max unit serial port clock cycle time sm2=0,12 clocks per cycle sm2=1,4 clocks per cycles 10 t xlxl 12 t clcl 4 t clcl ns ns output data setup to clock rising sm2=0,12 clocks per cycle sm2=1,4 clocks per cycles 10 t qvxh 12 t clcl 4 t clcl ns ns output data hold to clock rising sm2=0,12 clocks per cycle sm2=1,4 clocks per cycles 10 t xhqx 12 t clcl 4 t clcl ns ns input data hold to clock rising sm2=0,12 clocks per cycle sm2=1,4 clocks per cycles 10 t xhdx 12 t clcl 4 t clcl ns ns clock rising edge to input data valid sm2=0,12 clocks per cycle sm2=1,4 clocks per cycles 10 t xhdv 12 t clcl 4 t clcl ns ns figure 4 external clock drive waveform figure 5 ac testing input/output figure 6 ac testing, floating waveform test points 2.0v 0.8v 0.8v 2.0v notes: ac inputs during testing are driven at 2.4v for logic ?high? and 0.45v for logic ?low?. timing measurements are at 2.0v for logic ?high? and 0.8v for logic ?low? floating 2.0v 0.8v 0.8v 2.0v notes: the float state is define as the point which port 0 pins sinks 3.2ma or source 400 a at the voltage test level. t chcx t clcx 0.8v t clcl v ih1 t clch t chcl
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89t16r1 08/2006 12 ale /psen port0 port2 a0-a7 instr in a0-a7 a8-a15 a8-a15 a8-a15 a8-a15 t lhll t llpl t plph t llax t lliv t plaz t pxix t pxiz t pliv t avll t aviv1 t aviv2 figure 7 external program memory read cycle ale /psen /rd port0 port2 instruction in instruction in a0-a7 data in a0-a7 a8-a15 a8-a15 a8-a15 a8-a15 t llhl2 t lldv t aviv1 t aviv2 t avwl1 t avll t llwl t llax1 t rlrh t rldv t rlaz t rhdx t rhdz t whlh figure 8 external data memory read cycle ale /psen /wr port0 port2 instruction in instruction in a0-a7 data out a0-a7 a8-a15 a8-a15 a8-a15 a8-a15 t llhl2 t avwl1 t avll t llwl t wlwh t whlh t llax2 t qvwx t lwhqx t avdv2 figure 9 external data memory write cycle uart (synchronous mode) high speed operation sm2=1 => txd clock =xtal/4 ale /psen write_to_sbuf txd_data_out txd_clock ti write_to_scon_to_clean_ri rxd_data_in txd_clock ri d0 d1 d2 d3 d4 d5 d6 d7 d8 d0 d1 d2 d3 d4 d5 d6 d7 d8 t qvxh t xlxl t xhqx t xhdv t xhdx figure 10 uart mode 1timing
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89t16r1 08/2006 13 uart (synchronous mode) sm2=0 => txd clock =xtal/12 ale /psen write_to_sbuf txd_data_out txd_clock ti write_to_scon_to_clean_ri rxd_data_in txd_clock ri d0 d1 d6 d7 d0 d1 d6 d7 figure 11 uart mode 0 timing function description the sm89t16r1 is a high-speed (4 clocks/machine cycl e) stand-alone high-performance microcontroller designed for use in 3v/5v application, such as lcd monitor, instrumentation, or high-e nd consumer applications. in addition to the 80c51 standard func tions, the device provides a number of dedicated hardware functions for these applications. the sm89t16r1 is a control-oriented cpu with on-chip progr am and data memory. it can be extended with external data memory up to 64k bytes. for system requiring ex tra capability, the sm89t16r1 can be enhanced by using external memory and peripherals. the sm89t16r1 has two software selectable modes of saving power consumption-idle and power-down. the idle mode freezes the cpu while allowing the ram, timer, seria l ports and interrupt system to continue functioning. the power-down mode save the ram contents but freezes th e oscillator causing all other chip functions to be inoperative. the power-down mode can be terminated by h/w reset, or by any one of the six external interrupt or rtc function. cpu the cpu of sm89t16r1 is high-speed 80c51. the structure of this cpu is shown as figure 12. it contains instruction register (ir), instruction decoder, program counter (pc), accumulator (acc), b register, and control logic. this cpu provides an 8-bits bi-direction bus to communicate with other blocks in the chip. the address and data are transferred through on the same 8-bits bus.
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89t16r1 08/2006 14 figure 12 the cpu structure cpu timing the machine cycle consists of a sequence of 4 states, num bered s1 through s4. only one-oscillator periods for each state time. thus a machine cycle takes 4 oscillator periods . figure 13 shows relationships between oscillator, phase, and s1-s4. figure 13 sequences and phases figure 14 shows the fetch / execute sequences in states and phases for various kinds of instructions. normally the program fetches are generated during each machine cycle, ev en if the instruction being executed doesn?t require it. if the instruction being executed doesn?t need more code bytes, the cpu simply ignores the extra fetch, and the program counter is incremented accordingly. due to the reduced time for each instruc tion execution, both of the clocks edges are used for internal timing. hence it is important that the duty cycle of the clock be as close to 50% as possible to avoid timing conflicts. the sm89t16r1 dose one op-code fetch per machine cycle. therefore, in most of the instructions, the number of machine cycles needed to execute the instruction is equal to the number of bytes in the instruction. of the 256 available op-codes, 128 of them are signal cycle instruction. see figure14 shows the different cycle (a-d) instruction timing. alu ir q res cl k data in/out ctrl. bus prog. addr. power ctrl signal control logic timing & reset instruction decoder instruction register sp b re g iste r psw acc tmp1 tmp2 program addr.register buffer program increment program counter dptr pcon sequence s 1 s 2 s3 s 4 s 1 s 2 s 3 s 4 s 1 s 2 s3 s 4 machine cycle s 1 s 2 s3 s 4 s 1 s 2 s3 s 4 osc (xtal2) m1 m2 m3 m4 m5
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm89t16r1 08/2006 15 clk ale /psen ad7-0 port_2 a7-a0 data a15-a8 s1 s2 s3 s4 single_cycle b.) two cycles instruction timing clk ale /psen ad7-0 port_2 a7-a0 op-code a7-a0 operand a15-a8 a15-a8 s1 s2 s3 s4 instruction_fetch s1 s2 s3 s4 operand_fetch c.) three cycles instruction timing clk ale /psen ad7-0 port_2 a7-a0 op-code a7-a0 operand a7-a0 operand a15-a8 a15-a8 a15-a8 s1 s2 s3 s4 instruction_fetch s1 s2 s3 s4 s1 s2 s3 s4 operand_fetch operand_fetch d.) four cycles instruction timing clk ale /psen ad7-0 port_2 a7-a0 op-code a7-a0 operand a7-a0 operand a7-a0 operand a15-a8 a15-a8 a15-a8 a15-a8 s1 s2 s3 s4 instruction_fetch s1 s2 s3 s4 s1 s2 s3 s4 operand_fetch operand_fetch s1 s2 s3 s4 operand_fetch figure 14 timing of various instructions in standard 8032, the movx instructions take two machin e cycles to execute. however in the sm89t16r1, the user has a facility to stretch the duration of this instruction from 2 machines cycle to 9 machines. the /rd and /wr strobe lines are also proportionately elongated. this gives the u ser flexibility in accessing both fast and slow peripherals without the use of external circuitry and with minimum software overhead. see figure 15 a.) signal cycle instruction timing
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 16 a) data memory write with stretch value = 0(movx instruction execute 2 machine cycles) clk ale /psen /wr ad7-0 port_2 a7-a0 d7-d0 a7-a0 d7-d0 a7-a0 d7-d0 a7-a0 d7-d0 a15-a8 a15-a8 a15-a8 a15-a8 s1 s2 s3 s4 last_instruction s1 s2 s3 s4 s1 s2 s3 s4 first_machine_cycle second_machine_cycle s1 s2 s3 s4 next_instruction wr_width movx_instruction_cycle movx_inst._address movx_inst. next_inst._address next_inst._read movx_data_address movx_data_out b) data memory write with stretch value = 1(m ovx instruction execute 3 machine cycles)(default) clk ale /psen /wr ad7-0 port_2 a7-a0 d7-d0 a7-a0 d7-d0 a7-a0 d7-d0 a7-a0 d7-d0 a15-a8 a15-a8 a15-a8 a15-a8 s1 s2 s3 s4 last_instruction s1 s2 s3 s4 s1 s2 s3 s4 first_machine_cycle second_machine_cycle s1 s2 s3 s4 third_machine_cycle wr_width movx_inst._address movx_inst. next_inst._address next_inst._read movx_data_address movx_data_out s1 s2 s3 s4 next_instruction movx_instruction_cycle c) data memory write with stretch value = 2(movx instruction execute 4 machine cycles) clk ale /psen /wr ad7-0 port_2 a7-a0 d7-d0 a7-a0 d7-d0 a7-a0 d7-d0 a7-a0 d7-d0 a15-a8 a15-a8 a15-a8 a15-a8 s1 s2 s3 s4 last_instruction s1 s2 s3 s4 s1 s2 s3 s4 1'st_machine_cycle 2'nd_machine_cycle s1 s2 s3 s4 3'rd_machine_cycle wr_width movx_inst._address movx_inst. next_inst._address next_inst._read movx_data_address movx_data_out s1 s2 s3 s4 4'th_machine_cycle movx_instruction_cycle s1 s2 s3 s4 next_instruction figure 15: movx instruction timing (stretch=0~stretch=2)
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 17 instruction set the sm89t16r1 is high-speed 80c51; it?s contained 4 clocks per machine. the sm89t16r1 dose one op-code fetch per machine cycle .it consists of 111 instru ctions used 40 single-cycle, 38 used two-cycles, 19 used three-cycles, and 10 used four-cycles. a summary of the instruction set is given in table 4. addressing mode notes on instruction set and address modes: rn register r7-r0 of the curre ntly selected register bank. direct 8-bits internal data location?s address. this could be internal data ram location (0-127) or a sfr[i.e., i/o port, control register, status register, etc.(128-255) ] @ri 8-bits ram location addressed indirectly through register r1 or r0 of the actual register bank #data 8-bits constant included in the instruction #data16 16-bits constant included in the instruction addr11 11-bits destination address. used by acall and ajmp. the branch can be anywhere w ithin the same 2 kbytes page of program memory as the first by te of the following instruction. rel signed (2?s complement) 8-bits offset byte. used by sj mp and all conditional jumps. range is -128 to +127 bytes relative to first byte of the following instruction. bit direct addressed bit in internal data ram or sfr table 4: summary of the instruction mnemonic operation byte cycle arithmetic instructions add a,rn a = a + rn 1 1 add a,direct a = a + direct 2 2 add a,@ri a = a + <@ri> 1 1 add a,#data a = a + #data 2 2 addc a,rn a = a + rn + c 1 1 addc a,direct a = a + direct + c 2 2 addc a,@ri a = a + @ri + c 1 1 addc a,#data a = a + #data + c 2 2 subb a,rn a = a rn c 1 1 subb a,direct a = a direct c 2 2 subb a,@ri a = a <@ri> c 1 1 subb a,#data a = a #data c 2 2 inc a a = a + 1 1 1 inc rn rn = rn + 1 1 1 inc direct direct = direct + 1 2 2 inc @ri <@ri> = <@ri> + 1 1 1 dec a a = a 1 1 1 dec rn rn = rn 1 1 1 dec direct direct = direct 1 2 2 dec @ri <@ri> = <@ri> 1 1 1 inc dptr dptr = dptr + 1 1 1 dec dptr dptr = dptr 1 1 1 mul ab b:a = a b 1 1 div ab a = int (a/b),b = mod (a/b) 1 3 da a decimal adjust acc 1 1 logical instructions anl a,rn a .and. rn 1 1 anl a,direct a .and. direct 2 2 anl a,@ri a .and. <@ri> 1 1 anl a,#data a .and. #data 2 2 anl direct,a direct .and. a 2 2 anl direct,#data direct .and. #data 3 3 orl a,rn a .or. rn 1 1 orl a,direct a .or. direct 2 2 orl a,@ri a .or. <@ri> 1 1 orl a,#data a .or. #data 2 2 orl direct,a direct .or. a 2 2 orl direct,#data direct .or. #data 3 3
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 18 xrl a,rn a .xor. rn 1 1 xrl a,direct a .xor. direct 2 2 xrl a,@ri a .xor. <@ri> 1 1 xrl a,#data a .xor. #data 2 2 xrl direct,a direct .xor. a 2 2 xrl direct,#data direct .xor. #data 3 3 clr a a = 0 1 1 cpl a a = /a 1 1 rl a rotate acc left 1 bit 1 1 rlc a rotate left through carry 1 1 rr a rotate acc right 1 bit 1 1 rrc a rotate right through carry 1 1 swap a swap nibbles in a 1 1 data transfers instructions mov a,rn a = rn 1 1 mov a,direct a = direct 2 2 mov a,@ri a = <@ri> 1 1 mov a,#data a = #data 2 2 mov rn,a rn = a 1 1 mov rn,direct rn = direct 2 2 mov rn,#data rn = #data 2 2 mov direct,a direct = a 2 2 mov direct,rn direct = rn 2 2 mov direct,direct direct = direct 3 3 mov direct,@ri direct = <@ri> 2 2 mov direct,#data direct = #data 3 2 mov @ri,a <@ri> = a 1 1 mov @ri,direct <@ri> = direct 2 2 mov @ri,#data <@ri> = #data 2 2 mov dptr,#data16 dptr = #data16 3 3 movc a,@a+dptr a = code memory[a+dptr] 1 3 movc a,@a+pc a = code memory[a+pc] 1 3 movx a,@ri a = external memory [ri] (8-bits address) 1 2~9 movx a,@dptr a = external memory[d ptr] (16-bits address) 1 2~9 movx @ri,a external memory[ri] = a (8-bits address) 1 2~9 movx @dptr,a external memory[dptr] = a (16-bits address) 1 2~9 push direct inc sp: mov ?@?sp?, < direct > 2 2~9 pop direct mov < direct >, ?@sp?: dec sp 2 2~9 xch a,rn acc and < rn > exchange data 1 1 xch a,direct acc and < direct > exchange data 2 2 xch a,@ri acc and < ri > exchange data 1 1 xchd a,@ri acc and @ri exchange low nibbles 1 1 boolean instructions clr c c = 0 1 1 clr bit bit = 0 2 2 setb c c = 1 1 1 setb bit bit = 1 2 2 cpl c c = /c 1 1 cpl bit bit = /bit 2 2 anl c,bit c = c .and. bit 2 2 anl c,/bit c = c .and. /bit 2 2 orl c,bit c = c .or. bit 2 2 orl c,/bit c = c .or. /bit 2 2 mov c,bit c = bit 2 2 mov bit,c bit = c 2 2 jc rel jump if c= 1 2 3 jnc rel jump if c= 0 2 3 jb bit,rel jump if bit = 1 3 4 jnb bit,rel jump if bit = 0 3 4 jbc bit,rel jump if c = 1 3 4 jump instructions jz rel jump if a = 0 2 3 jnz rel jump if a 0 2 3 jmp @a+dptr jump to a+ dptr 1 2
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 19 djnz ri,rel decrement and jump if rn not zero 2 3 djnz direct,rel decrement and jump if direct not zero 3 4 cjne a,direct,rel jump if a < direct > 3 4 cjne a,#data,rel jump if a < #data > 3 4 cjne @ri,#data,rel jump if rn < #data > 3 4 cjne ri,#data,rel jump if @ri < #data > 3 4 acall address11 call subroutine only at 2k bytes address 2 3 ajmp address11 jump only at 2k bytes addressing 2 3 lcall address16 call subroutine in max 64k bytes address 3 4 ljmp address16 jump to max 64k bytes address 3 4 sjmp rel jump on at 256 bytes 2 3 ret return from subroutine 1 3 reti return from interrupt 1 3 nop no operation 1 1 memory organization program memory the program memory of sm89t16r1 consists of 64k byt es flash memory on chip. if during reset, the /ea pin was held high, the sm89t16r1 does not execute out of the internal program memory. if the /ea pin was held low during reset the sm89t16r1 fetch all instruc tions from the external program memory. internal data memory the data memory of sm89t16r1 consists of 1280 bytes internal data memory (256 bytes standard ram and 1024 bytes aux-ram). the aux-ram is enable by sconf.1 ($bf.1 ), and read/write by movx (stretch=0, 2 machine fixed) analog to digital converter (adc) the adc block diagram shown as below: those are only 4 pins mirror to port 2[7:4] at vin<3:0>. the digital output data [7:0] were put into adcd ($8fh). and the adc interrupt vector is 4bh. the adc sfr is shown as below: adscr ($8eh) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 com con adcss1 adcss0 ch1 ch0 com: read only. when convers ion complete, it will be set. con: when set, the adc will conversion c ontinuous, else it will conversion only once. adcss [1:0]: adc clock select. (adc_clk range 500 khz~2.5 mhz).if over frequency of adc_clk, the conversion data may be unstable. adcss1 adcss0 adc_clk 0 0 fosc/4 0 1 fosc/8 1 0 fosc/16 1 1 fosc/32 ch [1:0]: adc channel select. ch1 ch0 input select 0 0 ch0 0 1 ch1 1 0 ch2 1 1 ch3 adcd ($8fh) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ad.5 ad.4 ad.3 ad.2 ad.1 ad.0
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 20 6-bit sar adc vss vdd(=vref) adc_clk 4 vain<3:0>{p2.4~p2.7} ch<2:0>{adscr[3:2]} 3 6 data<5:0> {adcd[7:2]} adcss1 adcss0 adc_clk 0 0 f osc/4 0 1 f osc/8 1 0 f osc/16 1 1 f osc/32 adcss[1:0]= {adscr[5:4]} continuous{adscr.6} complete {adscr.7} figure 16 adc block diagram dual uart serial port in the sm89t16r1 is a full duplex port. the sm89t16r1 provides the user with additional features such as the frame error detection and the automatic address r ecognition. the serial ports are capable of synchronous as well as asynchronous communication. in synchronous mode the sm89t16r1 generates the clock and operates in a half duplex mode. in the asynchronous mode, full duplex opera tion is available. this means that it can simultaneously transmit and receive data. the transmit register and the receive buffer are both addressed as sbuf special function register. however any write to sbuf will be to the transm it register, while a read from the receive buffer register. the serial port can operate in four different modes as described below. mode 0 this mode provides synchronous communication with external devices. in this mode serial data is transmitted and received on the rxd line. txd is used to transmit the sh ift clock. the txd clock is provided by the sm89t16r1 whether the device is transmitting or receiving. this mode is therefore a half duplex mode of serial communication. in this mode, 8 bits are transmitted or received per frame. the lsb is transmitted / received fi rst. the baud rate is fixed at 1/12 or 1/4 of the oscillator frequency. this baud rate is determined at the sm 2 bit (scon.5). when this bit is set to 0, then the serial port runs at 1/12 of the clock. when set to 1, the serial port runs at 1/4 of the clock. this additional facility of programmable baud rate in mode 0 is the only difference between the sta ndard 8051 and the sm89t16r1. the function block diagram is shown belo w. data enters and leaves the serial port on the rxd line. the txd line is used to output the shift clock. the shif t clock is used to shift data into and out of the sm89t16r1 and the device at the other end of the line. any instruction that causes a write to sbuf will start the transmission. the shift clock will be activated and data will shifted out on the rxd pin till all 8 bits are transmitted. if sm2 = 1, then the data on rxd will appear 1 clock period before the fa lling edge of shift clock on txd. the clock on txd then remains low for 2 clock periods, and then goes high again. if sm2 = 0, the da ta on rxd will appear 3 clock periods before the falling edge of shift clock on txd. the clock on txd then remain s low for 6 clock periods, and then goes high again. this ensures that at the receiving end the data on rxd line can e ither be clocked on the rising edge of the shift clock on txd or latched when the txd clock is low. the ti flag is set high following the end of transmission of the last bit. the serial port will receive data when ren is 1 and ri is zero. the shift clock (txd) will be activated and the serial port will latch data on the rising edge of the shift clock. the external device should therefore present data on the falling edge on the shift clock. this process continues till all the 8 bits have been re ceived. the ri flag is set following the last rising edge of the shift clock on txd. this will stop reception, till the ri is cleared by software.
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 21 serial port mode 0: mode 1 in mode 1, the full duplex asynchronous mode is used . serial communication frames are made up of 10 bits transmitted on txd and received on rxd. the 10 bits consist of a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive; the stop bit goes into rb8 in the sfr scon. the baud rate in this mode is variable. the serial baud can be programmed to be 1/16 or 1/32 of the timer 1 overflow . since the timer 1 can be set to different reload values, a wide variation in baud rates is possible. transmission begins with a write to sbuf. the serial data is brought out on to txd pin following the first rollover of divide by 16 counter. the next bit is placed on txd pin follo wing the next rollover of the divide by 16 counter. thus the transmission is synchronized to the divide by 16 counter and not directly to the write to sbuf signal. after all 8 bits of data are transmitted the stop bit is transmitted. the ti flag is set after the stop bit has been put out on txd pin. this will be at the 10th rollover of the di vide by 16 counter after a write to sbuf. reception is enabled only if ren is high. the serial port actua lly starts the receiving of ser ial data, with the detection of the falling edge on the rxd pin; the 1-to-0 detector con tinuously monitors the rxd line, sampling it at the rate of 16 times the selected baud rate. when a falling edge is detect ed, the divide by 16 counter is immediately reset. this helps to align the bit boundaries with the rollovers of the divide by 16 counter. the 16 states of the counter effectively divide the bit time in to 16 slices. the bit detection is done on a best of three bases. the bit detector samples the rxd pi n, at the 8th, 9th and 10th counter states. by using a majority 2 or 3 voting system, the bit value is selected. this is done to improve the noise rejection feature of the serial port. if the first bit detected after the falling edge of rxd pin is not 0, then this indicates an invalid start bit, and the reception is immediately aborted. the serial port again looks for a falling e dge in the rxd line. if a valid start bit is detected, then the rest of the bits are also detected and shifted into the sbuf. after shifting in 8 data bits, there is one more shift to do, after which the sbuf and rb8 are loaded and ri is set. however certain conditions must be met before the loading and setting of ri can be done. ri must be 0 and either sm2 = 0, or the received stop bit = 1. if these conditions are met, then the stop bit goes to rb8; th e 8 data bits go into sbuf and ri is set. otherwise the received frame may be lost. after the middle of the stop bit, the receiver goes back to looking for a 1-to-0 transition on the rxd pin. /ri ren txd p3.1 alternate in p ut function serial port interru pt cloc k parin sout load rxd p3.0 alternate in p ut function transmit shift re g iste r tx start tx cloc k rx cloc k rx start tx shift rx shift load sbuf shift cloc k ri ti serial control internal data bus write to sbuf sbuf receive shift registe r cloc k parout sin rxd p3.0 alternate in p ut function internal data bus read sbuf sbuf clock source mode input 1/4 osc/1 1/64 osc/16 1/1024 osc/256 1/12 1/4 sm2 0 1
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 22 serial port mode 1: mode 2 this mode uses a total of 11 bits in asynchronous full- duplex communication. the functional description is shown in the figure below. the frame consists of one start bit (0), 8 data bits (lsb first), a programmable 9th bit (tb8) and a stop bit (0). the 9th bit received is put into rb8. the baud rate is programmable to 1/32 or 1/64 of the oscillator frequency, which is determined by the smod bit in pc on sfr. transmission begins with a write to sbuf. the serial data is brought out on to txd pin following the first rollover of the divide by 16 counter. thus the transmission is synchronized to the divide by 16 counter, and not directly to the write to sbuf signal. after all 9 bits of data are transmitted the stop bit is transmitted. the ti flag is set afte r the stop bit has been put out on txd pin. this will be at the 11th rollover of the divide by 16 counter after a wr ite to sbuf. reception is enabled only if ren is high. the serial port actually starts the receiving of serial data, with the detection of a falling edge on the rxd pin. the 1-to-0 detector continuously monitors the rxd line, sampling it at the rate of 16 times the selected baud rate. when a falling edge is detected, the divide by 16 counter is immediat ely reset. this helps to alig n the bit boundaries with the rollovers of the divide by 16 counter. the 16 states of the c ounter effectively divide the bit time into 16 slices. the bit detection is done on a best of three bases. the bit detector samples the rxd pin, at the 8th, 9th and 10th counter states. by using a majority 2 of 3 voting system, the bit value is selected. this is done to improve the noise rejection feature of the serial port. if the first bit detected after the falling edge of rxd pin, is not 0, then this indicates an invalid start bit, and the reception is immediately aborted. the serial port again looks for a falling edge in the rxd line. if a valid start bit is detected, then the rest of the bits are also detected and shif ted into the sbuf. after shifting in 9 data bits, there is one more shift to do, after which the sbuf and rb8 are loaded and ri is set. however certain conditions must be met before the loading and setting of ri can be done. ri must be 0 and either sm2 = 0, or the received 9th bit = 1. if these conditions are met, then the 9th bit goes to rb8, th e 8 data bits go into sbuf and ri is set. otherwise the received frame may be lost. after the middle of the stop bit, the receiver goes back to looking for a 1-to-0 transition on the rxd pin. 1 txd p3.1 alternate in p ut function serial port interru pt tx start tx cloc k rx cloc k rx start tx shift rx shift load sbuf shift cloc k ri ti serial control cloc k parin sout load rxd p3.0 alternate in p ut function t ransmit shift re g iste r internal data bus write to sbuf stop start sbuf receive shift re g iste r cloc k parout sin rxd p3.0 alternate in p ut function internal data bus read sbuf sbuf d8 rb8 bit detector timer 1 overflow 1/2 1/16 smod= ( smod 1 ) 0 1 timer 2 overflow ( for serial port 0 onl y) 1/16 rcl k 0 1 1- to-0 detector tcl k sample
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 23 serial port mode 2: mode 3 this mode is similar to mode 2 in all respects; expect that the baud rate is programmable. the user must first initialize the serial related sfr scon before any communication can take place. this involves selection of the mode and baud rate. the timer 1 should also be initialized if modes 1 a nd 3 are used. in all four modes, transmission is started by any instruction that uses sbuf as a destination register . reception is initiated in mode 0 by the condition ri = 0 and ren = 0. this will generate a clock on the txd pin and shift in 8 bits on the rxd pin. reception is initiated in the other modes by the incoming start bit if ren = 1. the external device will start the communication by transmitting the start bit. pulse width modulation (pwm) the pwm output pins are p1.4 and p1.5. the pwm clock is {fosc/ (2xdivider)}, the pwm output frequency is {(pwm clock)/32} at 5 bits resolution and {(pwm clock)/256} at 8 bits resolution. the pwm sfr is shown as below: pwmc ($d3h and $d4h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pbs pfs1 pfs0 pbs: when set, the pwm is 5 bits resolution. pfs [1:0]: the pwm clock divider select. pfs1 pfs0 pwm clock divider select 0 0 1 0 1 2 1 0 4 1 1 8 rxd p3.0 alternate in p ut function sample write to sbuf txd p3.1 alternate in p ut function serial port inte r ru pt sbuf receive shift re g iste r cloc k parout sin rxd p3.0 alternate in p ut function internal data bus read sbuf sbuf d8 rb8 bit detecto r clock source mode input 1/4 osc/2 1/64 osc/32 1/1024 osc/512 1/2 1/16 smod= ( smod 1 ) 0 1 1/16 1- to-0 detecto r cloc k parin sout load internal data bus stop start tx start tx cloc k rx cloc k rx start tx shift rx shift load sbuf shift cloc k ri ti serial control d8 tb8 transmit shift register
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 24 pwmd ($b3h and $b4h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pwmd.7 pwmd.6 pwmd.5 pwmd.4 pwmd.3 pwmd.2 pwmd.1 pwmd.0 real time clock (rtc) the on-chip rtc keeps time of second and minute functions. its time base is a 32.768 khz crystal between pins x32out (alternate function of ale) and x32in (alternate function of psen). the rtc maintains time to a second. it also allows a user to read or write values of seconds and minute. the rtc function used sfr descriptor as below: rtcs ($a1h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rtcen stable sec.5 sec.4 sec.3 sec.2 sec.1 sec.0 rtcen: when set to ?1?, enable the enable rtc functi on. when this bit set, the ale and psen pins output will disable, and the ale and psen pins will u se for rtc function as x32out and x32in. stable: read only. the stable bit will set to 1 when the rtc module stable. please wait 2 seconds before used the rtc function. sec [5:0]: show the current second counter at rtc function. the range is from 00h to 3bh. rtcc ($a2h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_sel1 int_sel0 min.5 min.4 min.3 min.2 min.1 min.0 int_sel [1:0]: the interrupt distribution selection bit, the interrupt vector is 43h. 00: the interrupt is set as 0.5 second 01: the interrupt is set as 1 second 10: the interrupt is set as 30 second 11: the interrupt is set as 60 second min [5:0]: show the current minute counter at rtc function. the range is from 00h to 3bh. starting and stopping the rtc: rtcs ($a1h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rtcen stable sec.5 sec.4 sec.3 sec.2 sec.1 sec.0 the rtc function is enable by set the rtcs.7 (rtcen=1), then the ale and /psen pins will switch to x32out and x32in that for rtc function used, the ale and p sen signal output will disable; the crystal frequency is 32768hz. see figure 17. 1 2 j1 x32in ( /psen ) 1 r j2 x32out ( ale ) 1 rtcen sw 1 1 2 32768hz clock in y1 32768hz in c hip figure 17 the rtc crystal connect diagram the stable bit (rtcs.6) will set to 1 when the rtc modul e stable. the design is about 31.25msec; suggest waiting 2
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 25 second to use the rtc function. this bit will clear when rtcen bit set again. the sec [5:0] will show the second counter (range from 00h to 3bh), and the min [5:0] will show the minute counter (range from 00h to 3bh) of rtc function. this two register will clear when rtcen bit set. interrupt: the rtc can select each of 4 interrupt sources: 0.5 second, 1 second, 0.5 minute, and 1 minute. the interrupt vector is 43h, it?s can wake-up cpu from power-down mode. the interrupt functions are test at eac h test item. like the int0 to int5 are test in pdwu function, the rtc interrupt are test at rtc func tion test, the adc interrupt are test at adc function test. this test item is focus in the priority test and only checks the lower voltage by each crystal. the interrupt sfrs show as below: ie1 ($a9h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 eadc ertc ertc: when set to ?1?, enable the rtc interrupt. if you want to use the rtc interrupt function, must enable the ea bit in ie.7 and enable the ertc bit in ie1.2. eadc: when set to ?1?, enable the adc interrupt. if you want to use the adc interrupt function, must enable the ea bit in ie.7 and enable the eadc bit in ie1.3 rtcc ($a2h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_sel1 int_sel0 min.5 min.4 min.3 min.2 min.1 min.0 then select the interrupt distributi on in int_sel [1:0] in rtcc [7:6]. the rtc can select each of 4 interrupt sources: 0.5 second, 1 second, 0.5 minute, and 1 minute. the interrupt vector is 43h, it can wake-up cpu from power-down mode. ifr ($aah) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 adcif rtcif adcif: when interrupt occupy the adc interrupt flag (if r.3) will set, and the cpu will execute the interrupt subroutine at the interrupt vector 4bh. the adc interrupt flag must clear by software. rtcif: when interrupt occupy the rtc interrupt flag (ifr.2) will set, and the cpu will execute the interrupt subroutine at the interrupt vector 43h. the rt c interrupt flag must clear by software. ip1 ($b9h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 padc prtc the interrupt priority can be set at ip1.2 or ip1.3. padc: when set to ?1?, enable the adc interrupt priority. prtc: when set to ?1?, enable the rtc interrupt priority.
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 26 divider 2 int 1min sec4 min0 divider 2 int 1sec sec0 min4 sec5 5 bits shif register int out rtcen u2 74151 4 3 2 1 15 14 13 12 11 10 9 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 a b c g y y min1 sec1 divider 30 min5 second register int 0.5min sec2 32768hz clock in min2 int sel0 divider 16384 minute register 5 bits shif register sec3 int 0.5sec min3 int sel1 figure 18 the rtc block diagram led driving capability control this function is set the sink current more then 10ma for each pin, 26ma for whole port 0, 15ma for whole port 1 or whole port2 or whole port3 or whole port4, and total 71ma for whole chip. the sfr shown as below: port name sfr address iol(max) of pre port port0 $92h 26 ma port1 $93h 15 ma port2 $94h 15 ma port3 $95h 15 ma port4 $96h 15 ma power saving mode the sm89t16r1 has several features that help the user to control the power consum ption of the device. the powers saving features are basically the power do wn mode, economy mode and the idle mode of operation. idle mode the user can put the device into idle mode by writing 1 to the bit pcon.0. the instruction that sets the idle bit is the last instruction that will be executed before the device goes in to idle mode. in the idle mode, the clock to the cpu is halted, but not to the interrupt, timer and serial port bl ocks. this forces the cpu state to be frozen; the program counter, the stack pointer, the program status word, the a ccumulator and the other registers hold their contents. the ale and psen pins are held high during the idle state. the port pins hold the logical states they had at the time idle was activated. the idle mode can be terminated in two ways . since the interrupt controller is still active, the activation of any enabled interrupt can wake up the processor. this will automatically clear the idle b it, terminate the idle mode, and the interrupt service routine (isr) will be executed. after the isr, execution of the program will continue from the instruction that put the device into idle mode. the idle mode can also be exited by activating the reset. th e device can be put into reset either applying a high on the external rst pin or a power on reset condition. the external reset pin has to be held high for at least two machine cycles to be recognized as a valid reset. in the reset cond ition the program counter is reset to 0000h and all the sfrs are set to the reset condition. since the clock is already running there is no delay and execution start immediately. when the sm89t16r1 is exiting from an idle mode with a reset, the instruction following the one that put the device into idle mode is not executed. so there is no danger of unexpected writes.
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 27 the power down wake up (pdwu) function the device can be put into power down mode by writing 1 to bit pcon.1. the instruction that does this will be the last instruction to be executed before the device goes in to power down mode. in the power down mode, all the clocks are stopped and the device comes to a halt. all activ ity is completely stopped and the power consumption is reduced to the lowest possible value. in this state the ale and psen pins are pulled low. the port pins output the values held by their respective sfrs. the sm89t16r1 will exit the power down mode with a reset or by a rtc (real time clock) interrupt or by an external interrupts pin enabled as level detects. 1. an external reset can be used to exit the power down state. the high on rs t pin terminates the power down mode, and restarts the clock. the program execution will restart from 0000h. 2. an external interrupt pin and rtc interrupt can be used to exit the power down state wh en the external interrupt or rtc interrupt actives and provided the corresponding interrupt is enabled, while the global enable (ea) bit is set and the external input has been set to a level detect mode or rtc interrupt set. if these conditions are met, then the low level on the external pin or rtc interrupt re-starts the osc illator. then device executes th e interrupt service routine for the corresponding external interrupt or rtc interrupt. after the interrupt service routine is completed, the program execution returns to the instruction after the one that put the device into power down mode and continues from there. the status of external pins during idle and power down: mode program memory ale /psen port0 port1 port2 port3 port4 idle internal 1 1 data data data data data idle external 1 1 float data address data data power down internal 0 0 data data data data data power down external 0 0 float data data data data pcon ($87h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 smod smod0 pd idle smod: this bit set to ?1? to make the uart baud-rate double. smod0: this bit define the scon.7 and scon1.7 use as fe (fe1) or sm0 (sm0_1) pd: when set to ?1?, the mcu will into power down mode idle: when set to ?1?, the mcu will into idle mode ie ($a8h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ea es1 et2 es0 et1 ex1 et0 ex0 ea: when set to ?1?, enable interrupt global. es1: when set to ?1?, enable uart1 interrupt. et2: when set to ?1?, enable timer2 interrupt. es0: when set to ?1?, enable uart interrupt. et1: when set to ?1?, enable timer1 interrupt. ex1: when set to ?1?, enable external interrupt 1. et0: when set to ?1?, enable timer0 interrupt. ex0: when set to ?1?, enable external interrupt 0. ip ($b8h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pt2 ps0 pt1 px1 pt0 px0 pt2: timer2 interrupt priority. ps0: uart interrupts priority.
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 28 pt1: timer1 interrupt priority. px1: external interrupt 1 priority. pt0: timer0 interrupt priority. px0: external interrupt 0 priority. eip ($bah) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 px5 px4 px3 px2 px5: when set to ?1?, external interrupt 5 priorities. px4: when set to ?1?, external interrupt 4 priorities. px3: when set to ?1?, external interrupt 3 priorities. px2: when set to ?1?, external interrupt 2 priorities. eie ($abh) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ex5 ex4 ex3 ex2 ex5: when set to ?1?, enable external interrupt 5. ex4: when set to ?1?, enable external interrupt 4. ex3: when set to ?1?, enable external interrupt 3. ex2: when set to ?1?, enable external interrupt 2. tcon ($88h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tf1: timer 1 overflow flag. tr1: timer 1 run control bit. tf0: timer 0 overflow flag. tr0: timer 0 run control bit. ie1: external interrupt 1 edge flag. it1: interrupt 1 type control bit. ie0: external interrupt 0 edge flag. it0: interrupt 0 type control bit. ckcon ($8eh) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t2m t1m t0m md2 md1 md0 t2m: timer 2 clock select. when ?1? used divide by 4 clock; when ?0? used divide by 12 clock. t1m: timer 1 clock select. when ?1? used divide by 4 clock; when ?0? used divide by 12 clock. t0m: timer 0 clock select. when ?1? used divide by 4 clock; when ?0? used divide by 12 clock. md [2:0]: stretch movx selects bits md2 md1 md0 stretch value movx duration 0 0 0 0 2 machine cycles 0 0 1 1 3 machine cycles (default) 0 1 0 2 4 machine cycles 0 1 1 3 5 machine cycles 1 0 0 4 6 machine cycles 1 0 1 5 7 machine cycles 1 1 0 6 8 machine cycles 1 1 1 7 9 machine cycles
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 29 dual dptr function the dps.0 define the instruction of inc dptr and dec dptr are working in dptr0 or dptr1. dps ($a6h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dps dps = 1 the instruction of inc dptr and dec dptr are working in dptr1. = 0 the instruction of inc dptr and dec dptr are working in dptr0. dph ($83h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dpl ($82h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dph1 ($a5h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dpl1 ($a4h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 data sram the sconf.1 must set to ?1? to enable the expand 1024 by tes ram, and this expand ram area must read/write by using the movx instruction. sconf ($bfh) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 smod_1 pdwue ome alei smod_1: this bit set to ?1? to make the serial port 1 baud-rate double. pdwue: when set to ?1?, enable the pdwu function. ome: when set to ?1?, enable the 1024 bytes expanded ram. alei: when set to ?1?, it will stop ale clock output for emi reduce. power management mode (pmm) power management mode offers a complete scheme of re duced internal clock speeds that allow the cpu to run software but to use substantially less power. normally , during default operation, th e sm89t16r1 uses 4 clocks per machine cycle. thus the instruction cycle (machine cycl e clock) rate is clock/4. at 16 mhz crystal speed, the instruction cycle speed is 4 mhz. in power management mode (pmm) the instruction cycle (machine cycle clock) rate is clock/1024. at same 16 mhz crystal speed, the inst ruction cycle speed is 15.6 khz. the operation current is down from 20ma to 5ma. see table 5. table 5 full operation (4 clocks/machine cycl e) pmm (1024 cloc ks/machine cycle) crystal speed instruction rate/operation current instruction rate/operation current 11.0592 mhz 2.765 mhz/19.6 ma 10.8 khz/4.78 ma 16 mhz 4.0 mhz/20 ma 15.6 khz/5 ma 25 mhz 6.25 mhz/30 ma 24.4 khz/5.6 ma
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 30 economy mode the power consumption of microcontroller relates to ope rating frequency. the sm89t16r1 offers an economy mode to reduce the internal clock rate dynamically without exte rnal components. by default, one machine cycle needs 4 clocks. in economy mode, software can select 4, 64, or 1024 clocks per machine cycle. it keeps the cpu operating a acceptable speed but eliminates the power consumption. in the idle mode, the clock of the core logic is stopped, but all clocked peripherals such as timer are still running at a rate of clock/4. in the economy mode, all clocks peripherals run at the same reduced clocks rate as in core logic. so the economy mode may provide lower power consumption than idle mode. software invokes the economy mode by setting the appropriate bits in the sfrs. setting the bits cd0 (pmr.6), cd1 (pmr.7) decides the instruction cycle rate as below: pmr ($d1h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cd1 cd0 xtoff cd1 cd0 clocks/machine cycle 00 reserved 01 4 10 64 11 1024 change clock test internal rc oscillator and external crystal switching exif ($91h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ie5 ie4 ie3 ie2 xt/~rg ie5: when set to ?1?, external interrupt 5 flag. ie4: when set to ?1?, external interrupt 4 flag. ie3: when set to ?1?, external interrupt 3 flag. ie2: when set to ?1?, external interrupt 2 flag. xt/~rg: when set to ?1?, the mcu used external crystal. when clear to ?0?, the mc u used internal rc oscillator this selection of instruction rate is going to take effect af ter a delay of one instruction cycle. switching to divide by 64 or 1024 mode must first go from divide by 4 modes. th is means software cannot switc h directly between clock/64 and clock/1024 mode. the cpu has to return clock/4 m ode first, then go to clock/64 or clock/1024 mode. the sm89t16r1 allows the user to use internal rc oscillator instead of exte rnal crystal. setting the xt/~rg bit (exif.3) selects the crystal or rc oscillator as the cl ock source. when invoking rc oscillator in economy mode, software may set the xtoff bit to turn off the crystal amplifier for saving power. the cpu would run at the clock rate of approximately 2-4 mhz divided by 4, 64 or 1024. the rc oscillator is not precise so that cannot be invoked to the operation that needs the accurate ti me-base such as serial communication. if crystal amplifier is disabled and rc oscillator is present clock source, software must first clear the xtoff bit to turn on crystal amplifier before switch to crystal operation. pmr ($d1h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cd1 cd0 xtoff xtoff: external crystal off; if the xt/~rg bit set to 1, this bit (xtoff) don?t care.
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 31 xt/~rg xtoff internal clock source 00 internal rc oscillator 01 internal rc oscillator(ext-crystal off) 10 external crystal 11 external crystal the priority structure and vect or locations of interrupts: source flag priority level vector address external interrupt 0 ie0 1(highest) 03h timer 0 overflow tf0 2 0bh external interrupt 1 ie1 3 13h timer 1 overflow tf1 4 1bh uart interrupt ri+ti 5 23h timer 2 overflow tf2+exf2 6 2bh uart 1 interrupt ri_1+ti_1 7 33h rtc interrupt rtcif 8 43h adc interrupt adcif 9 4bh external interrupt 2 ie2 10 5bh external interrupt 3 ie3 11 63h external interrupt 4 ie4 12 6bh external interrupt 5 ie5 13(lowest) 73h t2mod ($c9h ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hc5 hc4 hc3 hc2 t2cr t2oe dcen hc5: hardware clear /int5 flag hc4: hardware clear /int4 flag hc3: hardware clear /int3 flag hc2: hardware clear /int2 flag t2cr: timer 2 capture reset. in the timer2 capture mode this bit enables/disables hardware automatically reset timer2 while the value in tl2 and th2 have been transferred into the capture register. t2oe: timer2 clock output enable bit. if set to 1, the timer2 clock will output to p1.0. dcen: down count enable. when set this bit then allo ws timer2 to be configured as an up/down counter. application reference xi x2 sm89t16r1 x'tal r c1 c2 note: oscillation circuit may differs with differ ent crystal or ceramic resonator in highe r oscillation frequency which was due to ea ch crystal or ceramic resonator has its own characteristics. user should check with the crystal or ceramic resonator manufacturer for appropriate value of external components. valid for sm89t16r1 x'tal 3mhz 6mhz 9mhz 12mhz c1 30 pf 30 pf 30 pf 22 pf c2 30 pf 30 pf 30 pf 22 pf r open open open open x'tal 16mhz 25mhz c1 30 pf 15 pf c2 30 pf 15 pf r open open
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 32 pdip 40l (600mil) package informatio n note: 1. refer to jedec std.ms-011(ac). 2. dimension d and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d and e1 are maximum plastic body size dimension include mold mismatch. 3. dimension b3 does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b3 dimension by more than 0.2mm . dimension in mm dimension in mil symbol min nom max min nom max a1 0.254 10 a2 3.683 3.810 3.937 145 150 155 b 0.356 0.500 0.660 14 20 26 b1 0.356 0.457 0.508 14 18 22 b2 1.016 1.270 1.524 40 50 60 b3 1.016 1.321 1.626 40 52 64 c 0.203 0.254 0.432 8 10 17 c1 0.203 0.254 0.356 8 10 14 d 52.07 52.2 52.32 2050 2055 2060 e 14.99 15.24 15.49 590 600 610 e1 13.69 13.87 13.94 539 546 549 e 2.540 100 eb 15.75 16.26 16.76 620 640 660 l 2.921 3.302 3.683 115 130 145 s 1.727 1.981 2.235 68 78 88 q1 1.651 1.778 1.905 65 70 75 0 10 0 10
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 33 plcc 44l package informatio n unit symbol inch(ref) mm(base) a 0.180(max) 4.572(max) a1 0.024 0.005 0.52 0.14 a2 0.105 0.005 2.667 0.127 b 0.018 + 0.004 - 0.002 0.457 + 0.102 - 0.051 b1 0.028 + 0.004 - 0.002 0.711 + 0.102 - 0.051 c 0.010(typ) 0.254(typ) d 0.690 0.010 17.526 0.254 d1 0.653 0.003 16.586 0.076 d2 0.610 0.020 15.494 0.508 e 0.690 0.010 17.526 0.254 e1 0.653 0.003 16.586 0.076 e2 0.610 0.010 15.494 0.254 e 0.050(typ) 1.270(typ) y 0.003(max) 0.076(max) 0~5 0~5
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 34 qfp 44l(10x10x2.0mm) package information note: 1. refer to jedc std.ms-022(ab). 2. dimension e1 do not include mold protrusion. allowable protrusion is 0.25mm per side.e1 are maximum plastic body size dimension include mold mismatch . 3. dimension b does not include dambar protrusion .allowable dambar protrusion shall not cause the lead width to exceed the maximum b3 dimension by more than 0.1 mm. dimension in mm dimension in mil symbol min nom max min nom max a 2.45 964 a1 0.05 0.15 0.25 2.1 6.0 9.6 a2 1.90 2.00 2.10 74.8 78.7 82.7 b 0.29 0.32 0.45 11.4 12.6 17.7 b1 0.29 0.30 0.41 11.4 11.8 16.1 c 0.11 0.17 0.23 4.3 6.7 9.1 c1 0.11 0.15 0.19 4.3 5.9 7.5 e 13.00 13.20 13.40 512 520 528 e1 9.90 10.00 10.10 390 394 398 e 0.800 31.5 l 0.73 0.88 1.03 28.7 34.6 40.6 l1 1.50 1.60 1.70 59.1 63.0 66.9 y 0.076 3 0 7 0 7
syncmos technologies international, inc. sm89t16r1 8-bits micro-controller with 64kb flash rom & 1kb ram & two uart & rtc & adc & pwm embedded specifications subject to change without notice contact your sales representatives for the most recent information. ver 2.1 sm89t16r1 08/2006 35 e mcu writer list company contact info programmer model number advantech 7f, no.98, ming-chung rd., shin-tien city, taipei, taiwan, roc web site: http://www.aec.com.tw tel:02-22182325 fax:02-22182435 e-mail: aecwebmaster@advantech.com.tw lab tool - 48xp (1 * 1) lab tool - 848 (1*8) hi-lo 4f, no. 20, 22, ln, 76, rui guang rd., nei hu, taipei, taiwan, roc. web site: http://www.hilosystems.com.tw tel:02-87923301 fax:02-87923285 e-mail: support@hilosystems.com.tw all - 11 (1*1) gang - 08 (1*8) leap 6th f1-4, lane 609, chunghsin rd., sec. 5, sanchung, taipei hsien, taiwan, roc web site: http://www.leap.com.tw tel:02-29991860 fax:02-29990015 e-mail: service@leap.com.tw leap-48 (1*1) su - 2000 (1*8) xeltek electronic co., ltd 338 hongwu road, nanjing, china 210002 web site: http://www.xeltek-cn.com tel:+86-25-84408399, 84543153-206 e-mail: xelclw@jlonline.com, xelgbw@jlonline.com superpro/2000 (1*1) superpro/280u (1*1) superpro/l+(1*1)

▲Up To Search▲

Price & Availability of SM89T16R1C25

	To Download SM89T16R1C25 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .